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? 2004 california micro devices corp. all rights reserved. 10/13/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 1 cm3132 preliminary triple linear voltage regula tor for ddr-i memory and cpu features ? fully integrated power solution for a cpu/soc core and ddr-i memory ics ? lowest system cost and smallest footprint with just three external output capacitors ? three linear regulators for v core (1.5a), v ddq (1.5a), and v tt (0.5a, source-sink) ?v ddq = 2.5v, v tt = v ddq /2 25mv ?v core is adjustable, with a default output of 1.5v ? over-temperature and reverse current protection ? overcurrent protection for all regulators ? psop-8 package with integrated heat spreader ? lead-free version available applications ? core cpu and ddr-i memory power for: ? set top boxes, dvd players, games ? digital tvs, flat panel displays ? printers, digital projectors ? embedded systems ? communications systems product description the cm3132 provides an integrated power solution for a cpu core and ddr-i memory for consumer and other embedded applications. it features three independent linear regulators for v core , v ddq and v tt supply regulation. the default voltage for v core is 1.5v. the sense_core pin can be tied to gnd for the default voltage, or through a resistor divider for setting the cpu core in the range 1.2v to 1.8v. v ddq is internally set to 2.50v and the v tt voltage is always half the v ddq voltage. a capacitor should be con- nected to each of the three outputs. there are two enable pins, en_core and en_ddr . when en_core is set high, the core regulator is disabled. when en_ddr is set high, the two ddr regulators are dis- abled to minimize overall system power dissipation when memory is in standby mode. these two enable pins allow power sequencing of the ddr and core regulator blocks independently. the cm3132 is available in a psop-8 package that has excellent thermal dissipation. it is available with optional lead-free finishing. v ref r r v ref sense_core v tt =1.25v v ddq = 2.5v v ddq regulator v tt regulator v core regulator v core en_ddr v cc en_core gnd c ddq ddr memory v ref =1.25v c core cpu core + i/o c vcc r3 r4 c tt enable ddr memory # enable core# 2.8v to 3.3v v ref r r v ref sense_core v tt v ddq v ddq regulator v tt regulator v core regulator v core en_ddr v cc en_core gnd typical application circ uit circuit schematic
? 2004 california micro devices corp. all rights reserved. 2 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 10/13/04 cm3132 preliminary ordering information note 1: parts are shipped in tape & reel form unless otherwise specified. package / pinout diagram note: this drawing is not to scale. 8-lead psop 1 2 3 4 8 7 6 5 v core v cc v ddq v tt sense_core gnd en_core en_ddr top view pin descriptions psop-8 name description lead 1v core v core output. 2v cc input supply. 3v ddq v ddq output. 4v tt v tt output for termination resistors or v ref 5 en_ddr enable ddr power. active low input. 6 en_core enable v core . active low input. 7 gnd ground reference. 8 sense_core sense input. adjusts v core output voltage using external re sistor divider. when tied to gnd, v core = 1.5v. pad gnd tied to ground reference. part numbering information leads package standard finish lead-free finish ordering part number 1 part marking ordering part number 1 part marking 8 psop-8 CM3132-02SB cm3132 02sb cm3132-02sh cm3132 02sh
? 2004 california micro devices corp. all rights reserved. 10/13/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 3 cm3132 preliminary specifications absolute maximum ratings parameter rating units esd (human body model) 2000 v pin voltages v cc en_core , en_ddr , sense_core v ddq , v tt [gnd - 0.6] to [+6.5] [gnd - 0.6] to [v cc + 0.6] [gnd - 0.6] to [v cc + 0.6] v v v storage temperature range -40 to +150 c operating temperature range ambient junction 0 to +85 0 to +125 c c standard operat ing conditions parameter rating units ambient operating temperature range 0 to +85 c 1. v ddq regulator ddr-i supply voltage v cc [v ddq + 0.3] to 3.6 v load current 0 to 1500 ma c cc , c ddq 10, 10 f 2. v tt regulator ddr-i supply voltage v ddq 2.3 to 2.8 v ddr-i load current 0 to 500 ma c tt 47 f 3. v core regulator core supply voltage v cc [v ddq or v core + 0.3] to 3.6 v ddr-i load current 0 to 1500 ma c core 10 f
? 2004 california micro devices corp. all rights reserved. 4 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 10/13/04 cm3132 preliminary specifications (cont?d) electrical operating characteristics (see note1) symbol parameter conditions min typ max units general parameters t over shutdown junction temperature - 150 - c t hyst junction temp hysterisis ic in shutdown - 25 - c i ccn normal mode v cc supply current en_ddr = logic "0", en_core =logic "0" 400 800 a i ccq shutdown mode v cc supply current en_ddr = logic "1", en_core =logic "1" 210 a i sense in sense_core input current v sense_core =0.6v 0.1 1.0 a v ih en_ddr , en_core input high threshold v core =3.3v 2.0 v v il en_ddr , en_core input low threshold v core =3.3v 0.4 v uvlo under voltage lock-out i ddq = 10ma 1.8 v t rise v ddq , v core rise time v cc = 3.3v, c load = 10 f0.5ms v ddq regulator parameters v cc min input voltage v ddq = 2.5v, i ddq = 1.5a, note 2 2.80 v v ddq def default output voltage i ddq = 0.01a, 2.8v v cc 3.6v, note 2 2.45 2.50 2.55 v v ddq ld load regulation t a = 25c, v cc = 3.3v, 0.01a i ddq 1.5a, note 2 --2.5% v ddq line line regulation t a = 25c, i ddq = 0.01a, 2.8v v cc 3.6v, note 2 -1.0 - 1.0 % e n ddq output noise voltage bw = 10hz - 100khz, c ddq = 10 f49 vrms i ddq lim current limit note 2 1.7 2.0 a i ddq sc short circuit current v ddq < 0.3v 0.5 a
? 2004 california micro devices corp. all rights reserved. 10/13/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 5 cm3132 preliminary note 1: all parameters specified at t a = 0c to +85c unless otherwise noted. note 2: note that the i ddq current specified is the load current output from the v ddq pin. v ddq also supplies current internally to the v tt regulator when it is sourcing curren t. the maximum source current can be up to 0.5a.the maximum total current from the v ddq regulator is the external v ddq current i ddq added to the maximum v tt sourcing current i tt . all load currents are specified as such, but the v ddq current limit is specified at a current just above the total maximum current. note 3: v core regulator only. refer to v ddq regulator parameters for v ddq regulator. note 4: v core = 1.15v x (1 + ) table 1: truth table for cm3132 v tt regulator parameters v tt output voltage range v ddq = 2.5v, i tt = 0.01a, i ddq = 0a 1.20 1.25 1.30 v v tt ref output voltage range v cc = 0v, v ddq = 2.500v, i tt = 0.01a 1.225 1.250 1.275 v v tt ld load regulation t a = 25c, v ddq = 2.5v, 0.01a i tt 0.5a -1.0 - 1.0 % e n tt output noise voltage bw = 10hz - 100khz, c tt = 10 f51 vrms i tt lim current limit 0.6 0.8 a i tt sc short circuit current v tt < 0.7v 0.3 a v core regulator parameters v cc min input voltage v core = 1.5v, i core = 1.5a, sense_core = 0v, note 3 2.2 v v core def default output voltage range v cc = 3.3v, i core = 0.01a, sense_core = 0v 1.45 1.50 1.55 v v core adj adjustable output voltage range v cc = 3.3v, sense_core from resistors r3 & r4, note 4 1.2 1.8 v v core ld load regulation t a = 25c, v cc = 3.3v, 0.01a i core 1.5 --2.5% v core line line regulation t a = 25c, 2.8v v cc 3.6v, i core = 0.01a -1.0 - 1.0 % e n core output noise voltage bw = 10hz - 100khz, c core = 47 f59 vrms i core lim current limit 1.7 2.0 a i core sc short circuit current v core < 0.3v 0.5 a vcc(1) en_ddr v ddq out v tt out 2.8v to 3.6v low v ddq v ddq / 2 x high 0v 0v electrical operating cha racteristics (cont?d) (see note1) r3 r4 ------- -
? 2004 california micro devices corp. all rights reserved. 6 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 10/13/04 cm3132 preliminary performance information power supply ripple rejection c cc = 10 f, v cc = 3.3v, i load = 50ma, psrr measured with 50mv pk-pk sin wave on v cc . figure 1. v core psrr (v core = 1.5v) figure 2. v ddq psrr (v ddq = 2.5v) 0 5 10 15 20 25 30 35 40 45 50 10 100 1000 10000 100000 frequency (hz) psrr (db) 0 5 10 15 20 25 30 35 40 45 50 10 100 1000 10000 100000 frequency (hz) psrr (db)
? 2004 california micro devices corp. all rights reserved. 10/13/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 7 cm3132 preliminary figure 3. v tt psrr (v tt = 1.25v) 0 10 20 30 40 50 60 10 100 1000 10000 100000 frequency (hz) psrr (db)
? 2004 california micro devices corp. all rights reserved. 8 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 10/13/04 cm3132 preliminary performance information (cont?d) typical thermal characteristics the overall junction to ambient thermal resistance ( ja ) for device power dissipation (p d ) consists prima- rily of two paths in series. the first path is the junction to the case ( jc ) which is defined by the package style, and the second path is case to ambient ( ca ) thermal resistance which is dependent on board layout. the final operating junction temperature for any set of con- ditions can be estimated by the following thermal equa- tion: t junc = t amb + p d ( jc ) + p d ( ca ) = t amb + p d ( ja ) when a CM3132-02SB (psop-8) is mounted on a double-sided printed circuit board with two square inches of copper allocated for "heat spreading," the resulting ja is 40 c/w. based on the over tempera- ture limit of 150 c with an ambient of 70 c, the avail- able power of this package will be: p d = = 2w pcb layout considerations the CM3132-02SB/sh has a heat spreader attached to the bottom of the psop-8 package in order for heat to be transferred more easily from the package to the pcb. the heat spreader is a copper pad of dimensions just smaller than the package itself. by positioning the matching pad on the pcb top layer to connect to the spreader during manufacturi ng, the heat will be trans- ferred between the two pads. the drawing below shows the recommended pcb layout. note that there are six vias on either side to allow the heat to dissipate into the ground and power planes on the inner layers of the pcb. vias can be placed underneath the chip, but this can cause blockage of the solder. the ground and power planes should be at le ast 2 sq in. of copper by the vias. it also helps dissi pation if the chip is posi- tioned away from the edge of the pcb, and not near other heat-dissipating devices. a good thermal link from the pcb pad to the rest of the pcb will assure the best heat transfer from the cm3132 package to ambi- ent, ja , of around 40 c/w. figure 4. recommended heat sink pcb layout 150 c70 c ? 40 c/ w -------------------------------------- -
? 2004 california micro devices corp. all rights reserved. 10/13/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 9 cm3132 preliminary application information other applications the cm3132 can be used without any external resis- tors if a core voltage of 1.5v is required, the sense_core pin is connected to gnd. in applications where a reference voltage (v ref ) is required, the v tt pin can be used. the v tt output pin has an error relative to v ddq /2 of up to 25mv, which is well within most ddr system specs of 50mv. this is because the v tt output internally tracks the v ddq output very closely due to the matched on-chip resis- tors r that tap down from the v ddq rail, and the low offset voltage of the v tt regulator. it is recommended that the v ref trace be connected directly to the v tt pin, as shown in figure 5 , to eliminate noise and ripple on the v tt trace caused by current switching. figure 5. minimal cost solution for cm3132 supplying ddr memory and core cpu. v ref r r v ref sense_core v tt =1.25v v ddq = 2.5v v ddq regulator v tt regulator v core regulator v core =1.5v en_ddr v cc en_core gnd c ddq v ref =1.25v c core c vcc c tt enable ddr memory enable core 2.8v to 3.3v ddr-i memory cpu core + i/o
? 2004 california micro devices corp. all rights reserved. 10 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 10/13/04 cm3132 preliminary application information (cont?d) figure 6. power dissipation calculations figure 7. power derating table v ref r r v ref sense_core v ddq regulator v tt regulator v core regulator en_ddr v cc en_core gnd c ddq v ref =1.25v, 0.5a max, c core c tt enable ddr memory enable core vcc ddr-i memory cpu core + i/o 0.1a continuous v core =1.5v, 1a max, 1a continuous v ddq =2.5v, 1a max, 1a continuous with 3.3v cc @ 1a (v ddq ), 0.1a (v tt ), 1a (v core ), p d = (3.3-2.5) * 1.05 + (2.5-1.25) * 0.1 + (3.3-1.5) * 1 = 0.84 + 0.125 + 1.8 = 2.765w with 3.0v cc @ 1a (v ddq ), 0.1a (v tt ), 1a (v core ), p d = (3.0-2.5) * 1.05 + (2.5-1.25) * 0.1 + (3.0-1.5) * 1 = 0.525 + 0.125 + 1.5 = 2.15w with 2.8v cc @ 1a (v ddq ), 0.1a (v tt ), 1a (v core ), p d = (2.8-2.5) * 1.05 + (2.5-1.25) * 0.1 + (2.8-1.5) * 1 = 0.315 + 0.125 + 1.3 = 1.74w 1 psop-8 ic drives 1-dimm single ch annel ddr-i and cpu core vcore rail cm3132-02 psop-8 p d = (vcc-2.5)*iddq + (2.5-1.25)*0.1 + (vcc-vcore)*icore p d - (vcc-2.5)*iddq - 0.125 = (vcc-vcore)*icore icore = [p d - (vcc-2.5)*iddq - 0.125] / (vcc-vcore) derating (degc/w) 40 40 40 40 40 40 40 40 40 ambient (degc) 85 85 85 60 60 60 40 40 40 max power (w) 1.6 1.6 1.6 2.3 2.3 2.3 2.8 2.8 2.8 vcc (v) 3.3 3.0 2.8 3.3 3.0 2.8 3.3 3.0 2.8 min vcore (v) 1.5 1.5 1.5 1.5 1.4 1.0 1.5 1.2 1.1 max iddq (a) 1.0 0.8 0.5 1.0 1.0 1.0 1.0 1.0 1.0 max icore (a) 0.4 0.7 1.0 0.7 1.0 1.0 1.0 1.0 1.4 derating (degc/w) 60 60 60 60 60 60 60 60 60 ambient (degc) 85 85 85 60 60 60 40 40 40 max power (w) 1.1 1.1 1.1 1.5 1.5 1.5 1.8 1.8 1.8 vcc (v) 3.3 3.0 2.8 3.3 3.0 2.8 3.3 3.0 2.8 min vcore (v) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.4 max iddq (a) 0.3 0.5 0.6 1.0 0.7 0.5 0.5 0.7 1.0 max icore (a) 0.4 0.5 0.6 0.3 0.7 0.9 0.7 1.0 1.0 derating (degc/w) 80 80 80 80 80 80 80 80 80 ambient (degc) 85 85 85 60 60 60 40 40 40 max power (w) 0.8 0.8 0.8 1.1 1.1 1.1 1.4 1.4 1.4 vcc (v) 3.3 3.0 2.8 3.3 3.0 2.8 3.3 3.0 2.8 min vcore (v) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 max iddq (a) 0.3 0.3 0.3 0.5 0.5 0.5 0.5 0.7 0.5 max icore (a) 0.2 0.4 0.5 0.3 0.5 0.7 0.5 0.6 0.8 t junc =t amb +p d *( ja ) p d =(t amb -t junc )/( ja ) ja =40 o c/w ja =60 o c/w ja =80 o c/w
? 2004 california micro devices corp. all rights reserved. 10/13/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 11 cm3132 preliminary mechanical details psop-8 mechanical specifications dimensions for cm3132 devices packaged in an 8- lead psop package with a heatspreader are shown below. * this is an approximate number which may vary. ** centered on package centerline. package dimensions for psop-8 package dimensions package psop-8 leads 8 dimensions millimeters inches min max min max a 1.30 1.62 0.051 0.064 a 1 0.03 0.10 0.001 0.004 b 0.33 0.51 0.013 0.020 c 0.18 0.25 0.007 0.010 d 4.83 5.00 0.190 0.197 e 3.81 3.99 0.150 0.157 e 1.02 1.52 0.040 0.060 h 5.79 6.20 0.228 0.244 l 0.41 1.27 0.016 0.050 x** 3.30 3.81 0.130 0.150 y** 2.29 2.79 0.090 0.110 # per tube 100 pieces* # per tape and reel 2500 pieces controlling dimension: inches mechanical package diagrams h top view l end view c e b a a1 seating plane side view 1234 8765 pin 1 e d h bottom view 1234 8765 x y y/2 x/2 marking d e heat slug

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